Cache management using a buffer for invalidation requests

Abstract

An invalidation buffer is associated with each cache wherein either multiple processors and/or multiple caches maintain cache coherency. Rather than to decode the addresses and interrogate the cache directory to determine if data requested by an incoming command is in a cache, the invalidation buffer is quickly checked to determine if the data associated with the requested data has been recently invalidated. If so and if the command is not intended to replace the recently invalidated data, then the tag and data array of the cache are immediately bypassed to save precious processor time. If lower level caches maintain the same cache coherency and are accessed only through an adjacent cache, then those lower level caches may also be bypassed and a cache miss can be directed immediately to memory. In a multiprocessor system, such as NUMA, COMA, SMP, where other processors may access different cache levels independent of the adjacent cache level, then each invalidation buffer is checked. If the data is not in the invalidation buffer, a speculative cache hit can be generated and transferred to the requesting processor or upper level cache for earlier processing or to reserve a cache block, respectively.