The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2003
Filed:
Jul. 11, 2000
Applicant:
Inventors:
Gregory J. Smith, Tucson, AZ (US);
Jeffrey P. Kotowski, Nevada City, CA (US);
William J. McIntyre, Wheatland, CA (US);
Assignee:
National Semiconductor Corporation, Santa Clara, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/300 ; G06F 1/100 ;
U.S. Cl.
CPC ...
G06F 1/300 ; G06F 1/100 ;
Abstract
A system and method for providing for on-chip configuration, control and testing of mixed signal circuitry within an integrated circuit. A dual signal interface conveys the serial data and clock signals used for controlling the enablement, disablement and operational modes of the synchronous circuitry responsible for such on-chip configuration, control and testing, thereby minimizing the amount of overhead, in terms of interface terminals needed, for providing such capability.