The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2003

Filed:

Mar. 14, 1994
Applicant:
Inventors:

Sung-Hee Cho, Suwon, KR;

Sang-Ki Hwang, Suwon, KR;

Hyong-Gon Lee, Suwon, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 1/604 ;
U.S. Cl.
CPC ...
G11C 1/604 ;
Abstract

A nonvolatile semiconductor integrated circuit having a cell array consisting of a plurality of memory strings each having first to N-th (N=2, 3, 4, . . . ) memory cell transistors of a NAND structure includes a plurality of first string select transistors connected in series to the first memory cell transistor, and a plurality of second string select transistors connected in series to the N-th memory cell transistor. One of the string select transistors serially connected to the first and N-th memory cell transistors has a control terminal connected to a ground connecting point, thus to have a ground select function as well as a string select function.


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Cho, Sung-Hee. (2003). Nonvolatile semiconductor memories with a nand logic cell structure (U.S. Patent No. 6650567). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6650567

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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