The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2003

Filed:

Nov. 19, 2001
Applicant:
Inventors:

Pierre-André Farine, Neuchâtel, CH;

Jean-Daniel Etienne, Les Geneveys-sur-Coffrane, CH;

Ruud Riem-Vis, Neuchâtel, CH;

Elham Firouzi, Ligerz, CH;

Assignee:

Asulab S.A., Marin, CH;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B 2/100 ;
U.S. Cl.
CPC ...
H03B 2/100 ;
Abstract

The numerically controlled oscillator ( ) is mounted in particular in a radiofrequency signal receiver which further includes means ( ) for receiving and shaping the radiofrequency signals, a correlation stage ( ) and a clock signal generator. The oscillator receives at one input a clock signal with a first frequency (CLK) which clocks the oscillator operations, and a binary word of several bits (Nb) to provide at one output at least an output signal (Mb) with a frequency determined as a function of said binary word and the clock signal. The oscillator includes a first accumulation stage ( ) for a first number of most-significant bits (Ob) of the binary word and a second accumulation stage ( ) for a second number of least-significant bits (Pb) of said binary word. The first accumulation stage is clocked at the first clock frequency (CLK) to supply the determined frequency output signal (Mb), while the second stage is clocked at a second clock frequency (CLK/N) N times lower than the first clock frequency. Output bits (Qb) or binary signals from the second stage are multiplied by N to be introduced at the input of the first stage every N cycles of the clock signal at the first frequency (CLK).


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