The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2003

Filed:

Jun. 10, 2002
Applicant:
Inventors:

Yoshimi Shioya, Tokyo, JP;

Yuhko Nishimoto, Tokyo, JP;

Tomomi Suzuki, Tokyo, JP;

Hiroshi Ikakura, Tokyo, JP;

Kazuo Maeda, Tokyo, JP;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/120 ; H01L 2/136 ; C30B 1/00 ;
U.S. Cl.
CPC ...
H01L 2/120 ; H01L 2/136 ; C30B 1/00 ;
Abstract

The present invention relates to a manufacturing method of a semiconductor device in which a barrier insulating film and a main insulating film having low relative dielectric constant are sequentially formed while a wiring mainly consisting of copper film is coated. Its constitution includes the steps of: forming the barrier insulating film on a substrate subject to deposition, in which an electric power having a first frequency (f ) is applied to a first film forming gas containing at least silicon-containing gas and oxygen-containing gas to transform said first film forming gas into plasma and to cause reaction; and forming the main insulating film having low relative dielectric constant on the barrier insulating film , in which an electric power having a second frequency (f ) higher than the first frequency (f ) is applied to a second film forming gas containing at least the silicon-containing gas and the oxygen-containing gas to transform the second film forming gas into plasma and to cause reaction.


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