The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2003
Filed:
May. 06, 1999
Michael J. Gay, Vaud, CH;
Motorola, Inc., Schaumburg, IL (US);
Abstract
A current sensing circuit ( ) for use in an ADSL interface circuit senses an input current (IL) flowing through a resistor (R ) and provides an image output signal at an output which is an image of the input current. The circuit comprises an input stage ( ) having a first input terminal for coupling to one terminal of the resistor (R ), a second input for coupling to the other terminal of the resistor and first ( ) and second ( ) output terminals, a first P-type current mirror ( ) having an input terminal, an output terminal and a supply terminal, the input terminal being coupled to the first output terminal ( ) of the input stage ( ) and the supply terminal being coupled to a first supply line, a second N-type current mirror ( ) having an input terminal, an output terminal and a supply terminal, the input terminal being coupled to the second output terminal ( ) of the input stage ( ) and the supply terminal being coupled to a second supply line and combining means ( ) coupled to the output terminals of the first and second current mirrors for combining the output signals at the output terminals of the first and second current mirrors to provide the image output signal. The circuit further comprises bias means (R , R ) for biasing the input stage to operate in class AB such that the input stage provides a transconductance which tends to increase with increasing level of the input current, and offset means (R , R , R ) for generating offset voltages in the first and second current mirrors which cause the gains of the current mirrors to tend to reduce with increasing level of the input current such that the combined gains of the input stage and the first and second current mirrors remain substantially independent of the level of the input current.