Digital tuner with optimized clock frequency and integrated parallel cic filter and local oscillator

Abstract

A digital tuner for maximizing tuning range for a particular intermediate frequency includes an analog to digital converter ( ) operating at an input clock frequency to sample an analog input signal ( ) and output a multi-bit digital word for each sample, a demultiplexer ( ) in communication with the analog to digital converter ( ) and a plurality of mixers ( ) to convert serial samples from the analog to digital converter ( ) to parallel samples for input to the mixers ( ) functioning as quadrature multipliers, local oscillators ( ) in communication with corresponding ones of the mixers ( ), and a parallel cascaded integrator comb filter ( ) in communication with the mixers ( ) for filtering and decimating the parallel samples, where the mixers ( ), the local oscillators ( ), and the filter ( ) operate at a frequency having adjacent harmonics substantially centered about the intermediate frequency. A method for determining an operating frequency for a digital tuner having an associated intermediate frequency to reduce clock harmonic interference includes determining a maximum frequency based on operating parameters of tuner elements, selecting a harmonic of the operating frequency based on the intermediate frequency and the maximum frequency, and selecting the operating frequency based on the intermediate frequency.