Packet-based integrated circuit dynamic random access memory device incorporating an on-chip row register cache to reduce data access latencies

Abstract

A packet-based dynamic random access memory (“DRAM”) device incorporating an on-chip row register cache which is functional to reduce the initial device latency, reduce “page miss” latency and reduce chip layout overhead by reducing bus sizes and the level of required multiplexing and demultiplexing compared to Rambus® Direct RDRAM™ (trademarks, of Rambus, Inc., Mountain View, Calif.) devices. In accordance with an embodiment of the present invention, the row register cache and a separate write path, or bus, are integrated into each DRAM bank serving to improve DRAM latency parameters and pipeline burst rate. The row register holds “read” data during burst reads to allow hidden precharge and same bank activation to minimize “page miss” latency. The faster pipelined burst rate simplifies Direct RDRAM multiplexer/demultiplexer logic and reduces internal data bus size by 50%.