The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2003

Filed:

Jan. 22, 2002
Applicant:
Inventors:

Takayuki Kurokawa, Tokyo, JP;

Hiroshi Sugawara, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 1/134 ;
U.S. Cl.
CPC ...
G11C 1/134 ;
Abstract

A level shifter ( ) that may provide a relatively high-speed operation in a level shifting mode and a non-level shifting mode has been disclosed. Level shifter ( ) may include a transistor (P ) providing a controllable current path between a voltage terminal ( ) and an output signal (TOUT) based on the logic level of an input signal (IN). Series connected transistors (P and P ) may provide a controllable current path between voltage terminal ( ) and output signal (TOUT) based on the logic level of an input signal (IN). Transistor (P ) may be enabled in a Vcc mode and may be disabled in a Vpp mode. In this way, an equivalent transistor width (WT) may be adjusted in accordance with a mode of operation and a transition time of output signal (TOUT) may be improved.


Find Patent Forward Citations

Kurokawa, Takayuki. (2003). Semiconductor level shifter circuit (U.S. Patent No. 6646918). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6646918

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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