The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2003

Filed:

Aug. 29, 2002
Applicant:
Inventor:

Jonathan Lamb, Ringwood, GB;

Assignee:

Semtech Corporation, Camarillo, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 2/500 ;
U.S. Cl.
CPC ...
G01R 2/500 ;
Abstract

A phase detection system allows the capture range, lock range and jitter tolerance to be extended beyond ±360°. The capture range for the phase detection system may be extended in programmable amounts up to several thousand clock cycles or can be set to any desired maximum capture range in steps of approximately 360°. The phase detection system circuit utilizes a coarse phase detector and a fine phase detector. The phase detection system uses the digital cycle slip counter phase detector to provide a wide phase capture and lock range for a large jitter tolerance. The phase detection system combines this detector with a fine phase measurement from a PFD (phase and frequency detector) for very accurate phase control and low output jitter. The PFD operates in the approximately ±540° range and provides overlap in response with a coarse phase detector using a digital cycle counter approach. The PFD allows the digital counter, used for coarse cycle slip tracking, to precondition the PFD so that the coarse and fine detectors work together with no dead-band and no conflict in responses.


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