The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6645841 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 11, 2003

Filed:

Nov. 16, 2001
Applicant:
Inventor:

Wayne Kever, Fort Collins, CO (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/144 ; H01L 2/166 ; H01L 2/148 ; H01L 2/150 ; G01R 3/126 ;
U.S. Cl.
CPC ...
H01L 2/144 ; H01L 2/166 ; H01L 2/148 ; H01L 2/150 ; G01R 3/126 ;
Abstract

Selective application of solder bumps in an integrated circuit package. Solder bumps are selectively applied in a solder bump integrated circuit packaging process so that portions of a circuit can be effectively disabled. The bumps may be selectively applied either to a die or to the substrate using multiple solder masks, one for each pattern of solder bumps desired or can be otherwise applied in multiple patterns depending upon which portions of the circuitry are to be active and which are to be disabled.


Find Patent Forward Citations

Kever, Wayne. (2003). Selective solder bump application (U.S. Patent No. 6645841). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6645841

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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