Signal processing circuit with timing recovery pll

Abstract

A signal processing circuit for processing a read signal corresponding to data read from a recording medium, such as a magnetic disc. The signal processing circuit detects a preamble data signal of the read signal. A decision feedback equalizer (DFE) generates a computation read signal by performing a predetermined computation on the read signal in accordance with a clock signal. The DFE generates first code data using the computation read signal. A code data generating circuit connected to the DFE compares the computation read signal with a first reference signal and generates second code data, which corresponds to the preamble data signal. A phase error detection circuit detects a phase error between the clock signal and the read signal using one of the first and second code data. A timing recovery PLL is connected to the phase error detection circuit and uses the detected phase error to generate the clock signal such that the phase of the clock signal matches the phase of the preamble data signal.