System and method for limited access to system memory

Abstract

A hardware latch for limiting access to protected system memory. An N-bit bus provides the instructions executed by the system to a combinatorial logic block ( ). The combinatorial logic block ( ) provides eight separate outputs and functions as a series of comparators. One input of each comparator is connected to the instruction bus, the other input of each comparator is hardwired to indicate the pattern that appears on the bus when a particular instruction is executed. The output from a given comparator is active when that particular instruction is applied to the instruction bus ( ). A counter ( ) counts the instructions and selects which output from the combinatorial logic block should be selected by multiplexer ( ). If the output of the multiplexer is logic false, the sequence of instructions is broken and the counter ( ) is reset. If the output of the multiplexer is logic true, the counter is allowed to continue incrementing. If the counter reaches eight, a flip-flop ( ) representing the hardware gate can be written to. The output of the flip-flop ( ) is gated with the write signal provided to the protected blocks to prevent the write operations when the gate is locked. Another logic gate ( ) is provided to reset the counter if the instructions are executed out of a section of memory other than one of the protected blocks.