The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 04, 2003
Filed:
Dec. 27, 2000
Ellen Marie Bauman, Rochester, MN (US);
David Lee Dosch, Rochester, MN (US);
Daniel Paul Wetzel, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and apparatus are provided for interrupt routing of peripheral component interconnect (PCI) adapters via device address mapping. A first processor complex includes a multifunction PCI to PCI bridge interface chip. A local PCI bus is coupled between a second processor complex and the multifunction PCI to PCI bridge interface chip. A host PCI bus is coupled between the multifunction PCI to PCI bridge interface chip and a second multifunction PCI to PCI bridge chip. A plurality of local area network (LAN) adapters are coupled to the second multifunction PCI to PCI bridge chip. The multifunction PCI to PCI bridge interface chip of the first processor complex includes interrupt mapping logic for mapping interrupts from the LAN adapters to PCI interrupts on the local PCI bus to the second processor complex. The multifunction PCI to PCI bridge interface chip of the first processor complex includes translation logic for translating a configuration cycle on the local PCI bus from the second processor complex to another configuration cycle on the host PCI bus and for translating a configuration cycle on the host PCI bus from the LAN adapters to another configuration cycle on the local PCI bus to the second processor complex. The multifunction PCI to PCI bridge interface chip of the first processor complex includes a bus number register for specifying a PCI bus number and a device translation register for specifies a translation value for each function of the multifunction PCI to PCI bridge interface chip for determining a device number of each of said plurality of local area network (LAN) adapters.