The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2003

Filed:

Sep. 25, 2002
Applicant:
Inventors:

Ryo Kamiya, Hamamatsu, JP;

Tomoaki Ando, Hamamatsu, JP;

Assignee:

Yamaha Corporation, Hamamatsu, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/710 ;
U.S. Cl.
CPC ...
G06F 1/710 ;
Abstract

A series of digital data to be filtered is divided into a plurality of frames, and f samples of the digital data of each of the frames are burst-transmitted via a computer bus. In transferring the digital data of any one of the frames, n samples of the digital data belonging to a next frame is transferred, along with the digital data of the one frame, to thereby transfer a time series of the digital data consisting of (f+n) samples that are more than the f samples contained in the one frame. Also, a set of k filter coefficients to be used for filtering arithmetic operations in the frame is burst-transmitted via the computer bus, where n≧k. Filtering arithmetic processor, such as a DSP, connected to the bus carries out filtering arithmetic processing using the transmitted f+n samples of the digital data and k coefficients, to provide filtered data corresponding to at least the number of samples for a single frame. The filtering arithmetic processing may itself be conducted at high speed asynchronously with a predetermined sampling cycle. Thus, the filtering arithmetic operations are performed intermittently on a frame-by-frame basis. By buffering the filtered data and outputting them with the predetermined sampling cycle, there are provided filtered outputs synchronous with the predetermined sampling cycle. Cross-fade synthesis (interpolation) between filtered data of adjoining frames can smoothly interconnect the filtered data of the frames.


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