Synchronous memory devices with synchronized latency control circuits and methods of operating same

Abstract

A first clock signal is processed to produce a second clock signal that lags the first clock signal by a first predetermined time and a third clock signal that leads the first clock signal by a second predetermined time. A synchronous read status signal generator circuit receives a read initiation signal indicative of initiation of a read operation and a read termination signal indicative of termination of the read operation. The synchronous read status signal generator circuit produces a transition in a read status signal in response to assertion of either of the read initiation signal or the read termination signal, and latches the read status signal responsive to the second clock signal to generate a synchronized read status signal. A latency signal generator circuit receives the synchronized read status signal and generates a latency control signal therefrom responsive to the third clock signal. Output of data from the memory device is controlled responsive to the latency control signal.