Semiconductor memory device including clock-independent sense amplifier

Abstract

A semiconductor memory device includes a memory cell array, a read control circuit, a row decoder, a column decoder, a sense amplifier, and a sense amplifier control circuit. The read control circuit produces a precharge signal to precharge a bit line of the memory cell array. The sense amplifier amplifies data read onto the bit line. In reading data from a memory cell, the sense amplifier control circuit enables the sense amplifier and inhibits entry of read data from a memory cell into the sense amplifier only for a fixed interval after a fixed time after the precharging signal has been negated. The sense amplifier control circuit allows entry of read data into the sense amplifier while the sense amplifier is being disabled.