The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2003

Filed:

Aug. 29, 2002
Applicant:
Inventors:

Ramamoorthy Ramesh, Silver Spring, MD (US);

Darrell G. Schlom, State College, PA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/912 ; H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ;
U.S. Cl.
CPC ...
H01L 2/912 ; H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ;
Abstract

A ferroelectric memory cell formed on a monocrystalline silicon underlayer, either an epitaxial silicon contact plug to a transistor source or drain or silicon gate region for which the memory cell forms a non-volatile gate. A conductive barrier layer of doped strontium titanate, whether cationically substituted, such by lanthanum or niobium for strontium and titanium respectively, or anionically deficient, is epitaxially grown over the silicon, and a lower metal oxide electrode layer, a ferroelectric layer and an upper metal oxide electrode layer are epitaxially grown on the barrier layer. No platinum barrier is needed beneath the ferroelectric stack. The invention can be applied to many other functional oxide materials of the Ruddlesden-Popper and devices including micromachined electromechanical (MEM) devices and ferromagnetic tri-layer devices.


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