The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 04, 2003
Filed:
Oct. 29, 2002
Min-Sang Kim, Seoul, KR;
Dong-Won Shin, Kyungki-do, KR;
Samsung Electronics Co., Ltd., Suwon, KR;
Abstract
A fabrication method for forming a semiconductor device having a fuse is provided. A substrate includes a cell array area, a peripheral circuit area and a global step difference between the cell array area and the peripheral circuit area. The substrate comprises a fuse formed in the peripheral circuit of the substrate. An interlayer insulating layer is formed on the global step difference. The global step difference is reduced by a cell open process. A multilevel metal interconnection including an intermetal insulating layer is formed on the resultant structure. During the cell open process and/or the process for forming the multilevel metal interconnection, the interlayer insulating layer and/or the intermetal insulating layer is partially removed to form a recess. A passivation layer is formed on the multilevel metal interconnection. A fuse opening is formed through the recess to expose the fuse. The etching amount for forming the fuse opening is significantly reduced by the partial removal of the interlayer insulating layer and/or the intermetal insulating layer.