The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6642130 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 04, 2003

Filed:

Dec. 18, 2002
Applicant:
Inventor:

Cheol Soo Park, Kyoungki-do, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/14763 ;
U.S. Cl.
CPC ...
H01L 2/14763 ;
Abstract

A method for fabricating a transistor comprises steps of forming a conductive well region, an isolation oxide layer, a first pad oxide layer, a conductive LDD (low doped drain) region and a source/drain region on a silicon substrate. A pad nitride layer is formed on the first oxide layer. A trench is fanned by etching the pad nitride layer, the first oxide layer, the source/drain region, and the LDD region. A second pad oxide layer is then formed on the source/drain region and LDD region. The LDD region and part of the well region are removed after removal of the second pad oxide layer. A gate is formed in the trench, and an interlayer insulating layer is formed on the resultant structure.


Find Patent Forward Citations

Park, Cheol. (2003). Method for fabricating highly integrated transistor (U.S. Patent No. 6642130). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6642130

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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