Non-volatile memory device having self-aligned gate structure and method of manufacturing same

Abstract

A method for manufacturing a non-volatile memory device including a self-aligned gate structure, and a non-volatile memory device manufactured by the same method, are provided. In the method for manufacturing a non-volatile memory device, a tunnel dielectric layer is formed on a semiconductor substrate. First floating gate patterns are formed on the tunnel dielectric layer. Mold patterns are formed on the first floating gate patterns to selectively expose predetermined portions of the first floating gate patterns. Floating gates are formed by removing the exposed portions of the first floating gate patterns using the mold patterns as a mask. Interlayer dielectric layer patterns are formed for insulating the floating gates from one another by filling gaps between the mold patterns. The mold patterns exposed between the interlayer dielectric layer patterns are formed using the interlayer dielectric layer patterns as an etching mask. A dielectric layer is formed on the floating gates exposed by the removal of the mold patterns, between the interlayer dielectric layer patterns. Control gates are formed, aligned with the floating gates, by filling gaps between the interlayer dielectric layer patterns on the dielectric layer.