The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 04, 2003
Filed:
Mar. 03, 1997
Applicant:
Inventors:
Richard S. Terrill, Sunnyvale, CA (US);
Donald F. Faria, San Jose, CA (US);
Assignee:
Altera Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 3/126 ;
U.S. Cl.
CPC ...
G01R 3/126 ;
Abstract
A high performance single package multi-chip module multiplies the logic density of the highest density monolithic programmable logic device (PLD). A dual-sided substrate carries multiple prepackaged PLDs on a top side and a field programmable interconnect (FPIC) die on a bottom side. The prepackaged PLDs and the ability to use the substrate as a burn-in vehicle for the FPIC die results in reliable and reworkable assembly process with minimized yield loss.