The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2003
Filed:
Mar. 12, 2001
Xianxin Li, Milpitas, CA (US);
Pericom Semiconductor Corp., San Jose, CA (US);
Abstract
Electro-static-discharge (ESD) protection of an integrated circuit chip is enhanced by an EOS protection circuit using external components. An external MOSFET is placed in series with the ground pin of the integrated circuit chip. The external MOSFET has a gate coupled to a power bus through a gate resistor, and is bypassed by an ESD capacitor. The external MOSFET turns on after a delay when power is applied during hot insertion. The delay is determined by a power-to-ground bypass capacitor. The time delay of the on stage of the MOSFET inhibits ground current generated by EOS voltage leaked from the power supply through parasitic resistances, capacitances, and inductances, preventing ESD-protection diodes inside the chip from burning out from this EOS pulses that occur during hot insertion. The ESD bypass capacitor shunts the initial ESD pulse to ground before the external MOSFET turns on.