The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2003
Filed:
Apr. 04, 2002
Kei-Kang Hung, Changhua, TW;
Ming-Dou Ker, Hsin Chu, TW;
Faraday Technology Corp., , TW;
Abstract
A semiconductor device with substrate-triggered ESD protection technique includes a guard ring, a first MOS transistor array, a second MOS transistor array and a substrate-triggered portion. The first MOS transistor array, the second MOS transistor array and the substrate-triggered portion are formed in a region surrounded by the guard ring, and the substrate-triggered portion is located between the first MOS transistor array and the second MOS transistor array. Therefore, when the ESD event occurs, the substrate-triggered portion can be used for biasing a base of at least one parasitic BJT in the first MOS transistor array and a base of at least one parasitic BJT in the second MOS transistor array to achieve uniform turn-on among the multiple fingers of MOS transistor array. By using this layout design, the MOS transistor array can have a high ESD robustness.