The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2003
Filed:
Jan. 11, 2002
Duc Q. Chau, San Jose, CA (US);
Brian S. Mo, Fremont, CA (US);
Fairchild Semiconductor Corporation, South Portland, ME (US);
Abstract
A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor ( ) with a metal gate ( ). A sacrificial gate layer is patterned to provide a self-aligned source mask. The source regions ( ) are thus aligned to the gate ( ), and the source diffusion provides a slight overlap ( ) for good turn-on characteristics and low leakage. The sacrificial gate layer is capable of withstanding the diffusion temperatures of the DMOS process and is selectively etchable. After the high-temperature processing is completed, the sacrificial gate layer is stripped and a metal gate layer is formed over the substrate, filling the volume left by the stripped sacrificial gate material. In one embodiment, a chemical-mechanical polishing technique is used to planarize the metal gate layer.