Optimization of a logic circuit having a hierarchical structure

Abstract

A method and device are disclosed for easy and proper optimization of a logic circuit having a hierarchical structure. A limit value storage unit stores in advance target delay values that are the limit values of delay times. A flip-flop extraction unit extracts flip-flops included in the logic circuit that is the object of optimization and that is stored in a logic circuit storage unit. A hierarchy modification unit traces the logic circuit in the opposite direction of signal flow from an external output terminal of the logic circuit or the input of an extracted flip-flop until reaching an external input terminal of the logic circuit or another flip-flop and then modifies the hierarchical structure of the logic circuit to a structure constituted by hierarchical circuits that are each including logic elements that were passed through and flip-flops that were reached. A hierarchical circuit merge unit joins hierarchical circuits that include the same flip-flop. A logic optimization execution unit optimizes each of the hierarchical circuits such that their delay times satisfy the target delay values.