System for launching data on a bus by using first clock for alternately selecting data from two data streams and using second clock for launching data thereafter

Abstract

A bus interface apparatus and method are implemented. A pair of data streams is generated from the stream of data to be launched onto a data bus. Each stream is staged along a corresponding data path that includes a plurality of storage elements. Each path feeds an input of a multiplexer (MUX). The output of the MUX drives the bus, and the MUX selects a data value for launching onto the bus in response to a signal derived from an internal bus clock. The internal bus clock is also used to generate a bus clock that is output to the bus along with the data. The period of the bus clock may be a preselected multiple of the period of a processor clock. The data is staged along the two data streams in response to clocking signals derived from the processor clock. Each of the clocking signals is qualified by a corresponding hold signal, that, when asserted, holds the clocking signals in a predetermined state. The hold signals are generated in response to a plurality of control signals that are used to select the ratio of bus clock period to processor clock period. The bus interface may be asynchronously started in response to a signal from the startup logic in the central processing unit (CPU).