The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2003
Filed:
Aug. 03, 1999
Regis Gaillard, La Gaude, FR;
Nicolas Chauve, Cagnes sur mer, FR;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A digital system has a host processor with a bus controller and peripherals ( )- ( ) interconnected by an interconnect bus 32 peripherals are share a common strobe line (nSTROBE[ ]) on an embodiment of the interconnect bus in a first subdomain. Additional sub-domains, such as sub-domain can be likewise connected to interconnect bus Additional strobe lines nSTROBE(n) are used to select a particular sub-domain in response to an address presented to bus controller by CPU An interconnect bus transaction is synchronized in background so that a current cycle is not delayed. A first write cycle is completed as a no-wait state transaction, while immediately following second write cycle is delayed while synchronization circuit completes the synchronization of the first write cycle. nSTROBE pulse indicates first write transaction while nREADY pulse indicates the completion of a no-wait state first write transaction nSTROBE indicates the beginning of the second write transaction while nREADY pulse indicates the completion of a wait stated write, transaction Synchronization of write transaction is completed in background by using nSTROBE pulses and without the need for a free running clock signal from the host.