The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2003

Filed:

Jan. 14, 2000
Applicant:
Inventors:

Wei-Ming Su, Taipai, TW;

Shin Yung Chen Banyan, Taipei, TW;

Yi-Lin Lai, Kee-Lung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/72 ;
U.S. Cl.
CPC ...
G06F 7/72 ;
Abstract

A multiplier for obtaining the product of elements in a Galois Field. The multiplier performs the multiplication of two n-bit elements, A(a , a , . . . , a , a , a , a ) and B(b , b , . . . , b , b , b , b ) in the Galois Field to yield the product C(c , c , . . . , c , c , c , c ), wherein n≧1 a (i=0˜n-1), b (j=0˜n-1), and c (k=O˜n-1) are all binary bits. The multiplier includes: an AND planer, for performing an AND logic operation of every bit a in A(a , a , . . . , a , a , a , a ) and every bit b in B(b , b , . . . , b , b , b , b ) to obtain (a b , a b , . . . , a b , a b , a b , . . . , a b , a b , a b , . . . , a b ); and an XOR planer, for performing an XOR logic operation of the output from the AND planer to obtain C(c , c , . . . , c , c , c , c ).


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