The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2003
Filed:
Oct. 05, 1999
Pietro Filoramo, Siracusa, IT;
Gaetano Cosentino, Catania, IT;
STMicroelectronics S.r.l., Agrate Brianza, IT;
Abstract
A method for reducing the settling time in PLL circuits, particularly for use in an RF transceiver, the PLL circuits including a phase comparator, a filter, a digital-analog converter and an adder that are suitable to produce in output a voltage (V ) for controlling a voltage-controlled oscillator provided by means of a varactor, the method including determining the dependency of the control voltage (V ) of the voltage-controlled oscillator on the frequency of a selected channel of a transmitter; and generating a law describing the variation of the output current (I ) of the digital-analog converter such that the voltage (V ) obtained from the output current of the digital-analog converter, added to an output voltage (V ) of said filter keeps the filter voltage (V ) constant in order to reduce the settling time of the PLL circuit as a selected channel varies.