The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2003

Filed:

Aug. 05, 1999
Applicant:
Inventor:

Stefan Ott, Munich, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03D 3/24 ;
U.S. Cl.
CPC ...
H03D 3/24 ;
Abstract

A clock synchronization system for synchronizing a first communications device and a second communications device to enable digital communication there between. A first device generates a first clock signal Fa. A second device generates a second clock signal Fb . The second device includes a first PLL circuit and a second PLL circuit. The first PLL circuit is adapted to increase Fa by a factor K to produce a signal Fak. The second PLL circuit is adapted to increase Fak by a factor L to produce a signal Fbn. The second PLL circuit is further adapted to decrease Fbn by a factor N to produce the signal Fb . The first PLL circuit and the second PLL circuit are adapted to adjust the values of K, L, and N such that a frequency lock is achieved between Fa and Fb . enabling digital communication between the first device and the second device without requiring a predetermined phase lock between Fa and Fb


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