The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2003

Filed:

Sep. 16, 1998
Applicant:
Inventors:

Takaharu Nakamura, Kanagawa, JP;

Kazuo Kawabata, Kanagawa, JP;

Kazuhisa Ohbuchi, Kanagawa, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B 1/69 ;
U.S. Cl.
CPC ...
H04B 1/69 ;
Abstract

An n-bit binary value corresponding to an amount of phase shift d is assigned to an SREG, and a shift operation is performed. An n-bit vector value corresponding to a decimal value “1” is assigned to an LAT as an initial value. Thereafter, the input from an SW is sequentially stored. An MUL performs a square operation within a Galois field GF (2 ) for the output of the LAT. A DBL performs a double operation within the Galois field GF (2 ) for the output of the MUL. The SW selects either of the outputs of the MUL and the DBL according to the output value from the MSB side of the SREG. After the shift operation and the latch operation are performed a number of times n, the n-bit output of the LAT is output as respective phase shift coefficients b through b .


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