The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2003

Filed:

May. 31, 2001
Applicant:
Inventors:

D. C. Sessions, Phoenix, AZ (US);

Robert J. Caesar, Jr., Duluth, GA (US);

Ivan Svestka, North Riverside, IL (US);

David R. Evoy, Tempe, AZ (US);

Timothy Pontius, Lake in the Hills, IL (US);

Mark Johnson, Elgin, IL (US);

Arjan Bink, Chicago, IL (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 7/00 ;
U.S. Cl.
CPC ...
H03M 7/00 ;
Abstract

In one example embodiment, data is transferred at high speeds over a parallel data bus without loss of data integrity by transferring the data encoded with the quantity of ones relatively the same as the quantity of zeroes. Consistent with one embodiment of the present invention, a bus-interface circuit encodes a set of X data bits into a set of Y data bits, where Y is greater than X. The encoding is implemented to approximately balance the number of ones and the number of zeroes in each set to be transmitted. A specific example application involves encoding the set of X data bits so that there is a balanced number of ones and zeroes in the set of Y data bits. In certain applications, the present invention is implemented to reduce current flow between transmitting and receiving modules and thereby reduce EMI, reduce the number of power pins required for the bus interface, and/or reduce the I/O delay and the skew from voltage sag in the signals passed over the parallel data bus.


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