The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2003
Filed:
Nov. 17, 2000
Applicant:
Inventors:
Seiji Narui, Hamura, JP;
Tetsu Udagawa, Iruma, JP;
Kazuhiko Kajigaya, Iruma, JP;
Makoto Yoshida, Ome, JP;
Assignee:
Hitachi, Ltd., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/7108 ; H01L 2/976 ; H01L 3/1119 ; H01L 2/348 ; H01L 2/352 ;
U.S. Cl.
CPC ...
H01L 2/7108 ; H01L 2/976 ; H01L 3/1119 ; H01L 2/348 ; H01L 2/352 ;
Abstract
The sheet resistance of a gate electrode A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL , BL are, respectively, 2 &OHgr;/□ or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode A (the word line WL) or the bit lines BL , BL by which the number of the steps of manufacturing the DRAM can be reduced.
Quick Actions:
Narui, Seiji. (2003). Semiconductor integrated circuit device and method for manufacturing the same (U.S. Patent No. 6635918). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6635918
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