Method for fabricating nor type flash memory device

Abstract

Disclosed is a method for fabricating a NOR flash memory device where a buried common source line made of an impurity diffusion layer has an even surface or a lower step difference. The method includes forming adjacent isolation layers that define an active region there between within a semiconductor substrate. Then, a floating gate pattern is formed overlying the active region. An inter-gate dielectric film and a control gate film are sequentially formed overlying the floating gate pattern. The control gate film, the inter-gate dielectric film, and the floating gate pattern are sequentially patterned, thereby forming a plurality of word lines extending across the active region. The active region between the adjacent isolation layers and the isolation layers are removed, adjacent to one sidewall of the word lines, thereby forming a common source line region. Next, impurities are implanted into the common source line region, thereby forming a common source line made of an impurity diffusion layer.