Apparatus and method for synchronizing a clock using a phase-locked loop circuit

Abstract

A system for synchronizing a clock includes a phase-locked loop (PLL) circuit that generates or receives ( ) timing errors that are based on timing information from multiple timing sources. Gain blocks ( ) weight ( ) the timing errors, which are then combined ( ) into a loop time error. A loop integrator ( ) integrates ( ) the loop time error to produce an input used to adjust ( ) an oscillator frequency. A corresponding oscillator clock signal is fed back ( ) to one or more phase detectors ( ), which receive ( ) timing reference signals and generate timing errors. When a timing errors indicates that a problem exists with a timing source, the impact of the problematic timing source is reduced ( ), or oscillator frequency adjustments are suspended ( ). When used on a satellite ( ), at least one of the timing errors can be based on times of transmit and times of arrival of time messages exchanged between the satellite and its neighbors ( ).