The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2003

Filed:

Mar. 23, 2001
Applicant:
Inventors:

Masato Kawata, Tokyo, JP;

Kuniko Kikuta, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/710 ; H01L 2/976 ; H01L 2/7108 ; H01L 2/18238 ; H01L 2/18234 ;
U.S. Cl.
CPC ...
H01L 2/710 ; H01L 2/976 ; H01L 2/7108 ; H01L 2/18238 ; H01L 2/18234 ;
Abstract

In a non-volatile semiconductor memory having a peripheral circuit zone and a memory zone including plural memory cells each having a floating gate and a control gate, an interlayer insulator is formed over the control gate of the memory cells and a gate electrode in the peripheral circuit zone. A groove is formed in the interlayer insulator film to longitudinally extend along a word line which constitutes the control gate for a plurality of memory cells arranged in one line. This groove penetrates through the interlayer insulator film to reach the word line over the whole length of the word line. A conducting material is deposited on the interlayer insulator film to fill up the groove so that a plate-shaped contact is formed in the groove. The conducting material is patterned to form an overlying interconnection extending on the interlayer insulator film along the word line.


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