Clock synchronization and fault protection for a telecommunications device

Abstract

A telecommunications device includes a synchronization bus and a controller coupled to the bus. The controller selects a primary reference clock signal from among a plurality of reference clock signals, generates a first system clock signal according to the primary reference clock signal, and communicates the system clock signal using the bus. The controller detects a loss of signal associated with the primary reference clock signal and, in response, enters holdover mode. The controller continues generating the first system clock signal while in holdover mode and determines the acceptability of a secondary reference clock signal also selected from among the plurality of reference clock signals. The controller performs a switchover from the primary reference clock signal to the secondary reference clock signal if the secondary reference clock signal is acceptable and, in response to the switchover, generates the first system clock signal according to the secondary reference clock signal. In one embodiment, a card coupled to the bus detects and indicates a loss of signal associated with the first system clock signal. A second controller determines a failure of the controller in response to at least the indication from the card. In a particular embodiment, the device is a switching unit having a high availability backplane environment.