Vliw computer processing architecture with on-chip dynamic ram

Abstract

A novel processor chip ( ) having a processing core ( ), at least one bank of memory ( ), an I/O link ( ) configured to communicate with other like processor chips or compatible I/O devices, a memory controller ( ) in electrical communication with processing core ( ) and memory ( ), and a distributed shared memory controller ( ) in electrical communication with memory controller ( ) and I/O link ( ). Distributed shared memory controller ( ) is configured to control the exchange of data between processor chip ( ) and the other processor chips or I/O devices. In addition, memory controller ( ) is configured to receive memory requests from processing core ( ) and distributed shared memory controller ( ) and process the memory request with memory ( ). Processor chip ( ) may further comprise an external memory interface ( ) in electrical communication with memory controller ( ). External memory interface ( ) is configured to connect processor chip ( ) with external memory, such as DRAM. Memory controller ( ) is configured to receive memory requests from processing core ( ) and distributed shared memory controller ( ), determine whether the memory requests are directed to memory ( ) on chip ( ) or the external memory, and process the memory requests with memory ( ) on processor chip ( ) or with the external memory through external memory interface ( ).