The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2003
Filed:
Sep. 04, 2001
Kazuo Kobayashi, Suwa, JP;
Seiko Epson Corporation, Tokyo, JP;
Abstract
The invention reduces capacitor coupling between data read bit lines and data write bit lines to thereby prevent error detection of data. A first pair of bit lines BM and {overscore (BM)} that read data from a specified one of memory cells in a memory cell column and a second pair of bit lines BS and {overscore (BS)} that write data in another specified one of the memory cells in the memory cell column are formed in different layers through an interlayer dielectric film. As viewed in a plan view, the space between the first pair of bit lines BM and {overscore (BM)} is wider than the second pair of bit lines BS and {overscore (BS)}, and the second pair of bit lines BS and {overscore (BS)} are disposed between the first pair of bit lines BM and {overscore (BM)}. A first wiring layer that is set a ground potential is disposed in the same layer as the first pair of bit lines BM and {overscore (BM)} and between the first pair of bit lines BM and {overscore (BM)}. Second and third wiring layers that are set at a ground potential are disposed in the same layer as the second pair of bit lines BS and {overscore (BS)} and opposite to the respective bit lines of the first pair of bit lines BM and {overscore (BM)} with the interlayer dielectric film being interposed therebetween.