Method of manufacturing 6f2 trench capacitor dram cell having vertical mosfet and 3f bitline pitch

Abstract

A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor extends down at least one side wall of the deep trench above the storage capacitor. The transistor has a source diffusion extending in the plane of the substrate adjacent the deep trench. An isolation extends down at least one other sidewall of the deep trench opposite the vertical transistor. Shallow trench isolation regions extend along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends. A gate conductor extends within the deep trench. A wordline extends over the deep trench and is connected to the gate conductor. A bitline extends above the surface plane of the substrate and has a contact to the source diffusion between the shallow trench isolation regions.