The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2003

Filed:

Dec. 14, 2000
Applicant:
Inventors:

Subbu Ganesan, Saratoga, CA (US);

Leonid Alexander Broukhis, Fremont, CA (US);

Ramesh Narayanaswamy, Mountain View, CA (US);

Ian Michael Nixon, Sunnyvale, CA (US);

Assignee:

Tharas Systems Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ; G06F 9/45 ;
U.S. Cl.
CPC ...
G06F 1/750 ; G06F 9/45 ;
Abstract

Functional verification system enabling the state of difference signals to be traced. The signals represent the outputs resulting from the evaluation of combinatorial blocks and/or a plurality of state elements forming a target design. The combinatorial blocks and/or a plurality of state elements may be grouped into multiple clusters, with each cluster being identified by a cluster identifier. The tracing circuit may include a mask memory, a previous state memory, and trace controller. Each of the mask memory and the previous state memory may contain a number of locations equal to the number of clusters such that the relevant mask and previous state information may be accessed based on the cluster identifier. The trace controller receives evaluated outputs for a cluster at bit positions specified by a corresponding mask. The trace controller compares the received bits with the previous values, and generates an entry in a trace buffer to record any changes.


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