The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 2003
Filed:
Apr. 28, 2000
Joseph A. Hoffman, Chandler, AZ (US);
Joseph W. Yoder, Oakton, VA (US);
BAE Systems Information and Electronic Systems Integration, Inc., Nashua, NH (US);
Abstract
A scannable flip flop for space-based LSSD testable integrated circuits. A scannable register can be formed from the scannable flip flops. The scannable flip flops can be radiation hardened. Each scannable flip flop can include a 2:1 input multiplexer, a first latch and a second latch. The input multiplexer is coupled to the first latch by a pair of pass gates. The pass gates are gated by a first clock input signal. A second pass gate pair couples the first latch to the second latch. A second clock input signal gates the second pass gate pair. The first and second clock input signals are non-overlapping. The latch can be employed in edge triggered logic ECAD tools for designing IC. The resulting IC logic can be tested using LSSD test testing techniques and patterns.