The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 2003
Filed:
Aug. 31, 2000
Applicant:
Inventor:
David Hartwell, Bolton, MA (US);
Assignee:
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/24 ;
U.S. Cl.
CPC ...
G06F 1/24 ;
Abstract
An initialization/reset circuit automatically resets and initializes a clocking subsystem having a phase locked loop (PLL) within a data processing system. The logic circuit is contained within an input/output (I/O) interface of the system. Clock signals are provided from a clock source of the data processing system to the PLL. In addition to the PLL, the initialization/reset logic circuit comprises a counter, a first timer circuit and a second watchdog timer.