The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2003

Filed:

May. 30, 2001
Applicant:
Inventors:

Takashi Hashimoto, Fukuoka, JP;

Yasuo Kohashi, Fukuoka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/200 ;
U.S. Cl.
CPC ...
G06F 1/200 ;
Abstract

In a host interface circuit performing data transmission/reception between an external host controller and a device connected to the external host controller, the external host controller generates, as external addresses to be supplied to the connected device, first addresses corresponding to the respective internal addresses in an internal storage space of the connected device, and a specific second address corresponding to internal addresses of a series of areas in the internal storage space; and the host interface circuit includes a first address conversion circuit for converting the first addresses into the internal addresses in the internal storage space, and a second address conversion circuit for converting the specific second address into the internal addresses in the internal storage space; and the specific second address is used when the external host controller makes continuous access to the serial areas in the internal storage space of the connected device. Therefore, the external host controller can make continuous access to a series of areas in the internal storage space of the connected device by using the specific address, without using DMA, between the external host controller and the host interface circuit. As the result, power consumption is reduced, and complexity in software processing is reduced.


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