Set-associative cache-management using parallel reads and serial reads initiated during a wait state

Abstract

A Harvard-architecture computer system includes a processor, an instruction cache, a data cache, and a write buffer. The caches are both set-associative in that they each have plural memories; both caches perform parallel reads by default. In a parallel read, all cache-memory locations of the selected cache corresponding to the set ID and word position bits of a requested read address are accessed in parallel while it is determined whether or not one of these locations has a tag matching the tag portion of the requested read address. If there is a “hit” (match), then an output multiplexer selects the appropriate cache memory for providing its data to the processor. The parallel read thus achieves faster reads, but expends extra power in accessing non-matching sets. A cache receiving a read request while the processor is waited performs a serial read instead of a parallel read. In a serial read, the tag match is performed before the data is accessed. Accordingly, a cache memory is accessed only if a match is found, achieving a power savings relative to a parallel read. There is no latency penalty since the parallel read cannot be completed during the wait. Thus, the power savings is achieved without impairing performance.