The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2003

Filed:

Nov. 08, 1999
Applicant:
Inventors:

Joel Roger Davidson, Austin, TX (US);

Michael Stephen Floyd, Leander, TX (US);

Paul Joseph Jordan, Austin, TX (US);

Judith E. K. Laurens, Bastrop, TX (US);

Alexander Erik Mericas, Austin, TX (US);

Kevin F. Reick, Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/300 ;
U.S. Cl.
CPC ...
G06F 1/300 ;
Abstract

A multi-stage byte lane selectable bus. In a preferred embodiment, the bus in performance monitor mode includes a plurality of byte lanes and a selection mechanism. The selection mechanism acquires, from a plurality of signals, a subset of those signals, which are desired to be monitored, and places this subset of signals on the byte lanes that are input to the PMU. The number of the plurality of signals that potentially may be monitored is greater than the number of byte lanes and is also greater than the number of PMU counters.


Find Patent Forward Citations

Davidson, Joel. (2003). Method and apparatus for a byte lane selectable performance monitor bus (U.S. Patent No. 6629170). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6629170

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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