The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2003

Filed:

Oct. 23, 2002
Applicant:
Inventors:

Susan Morton, Newbury Park, CA (US);

Albert Cosand, Agoura Hills, CA (US);

Assignee:

The Boeing Company, Chicago, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/45 ; H03F 3/217 ; H03F 1/02 ; H03K 5/00 ; H03M 1/12 ;
U.S. Cl.
CPC ...
H03F 3/45 ; H03F 3/217 ; H03F 1/02 ; H03K 5/00 ; H03M 1/12 ;
Abstract

A linearized folding amplifier circuit ( ) includes a comparator ( ) that has a first state and a second state, and a switched output circuit that has a pair of outputs. The non-linearity in the response of a differential transistor pair to an input signal is partially linearized by a first resistor connecting the emitters of the two input transistors. The input is further linearized in response to the first and second state-controlling pairs of transistors and a differential error voltage therebetween that is replicated from the differential error in the base-voltages emitter voltages of the input differential pair. The output of the circuit is the combination of the partially linearized portion from the first resistor and a linearized transconductor circuit that has an output formed in response to the differential error.


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