The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2003

Filed:

Feb. 07, 2002
Applicant:
Inventors:

Jung-Woo Park, Seoul, KR;

Uk-Rae Cho, Suwon, KR;

Nam-Seog Kim, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 ;
U.S. Cl.
CPC ...
H03L 7/06 ;
Abstract

An internal clock generating circuit and method for generating an internal clock phase-synchronized to an input clock with minimum delay and at high speed is disclosed. An internal clock generating circuit comprises a first delay control circuit for generating a first clock having the time delay of up to T/2 (where T is a cycle of an input clock) from the input clock and for generating a first variable delay control signal; and a second delay control circuit for generating a second clock in response to the first variable delay control signal, the second clock having the time delay of greater than T/2 from the input clock at an initial state and having the time delay of about T from the input clock in a phase-locked state.


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