The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 2003
Filed:
Feb. 20, 2001
William T. Cochran, Clermont, FL (US);
Isik C. Kizilyalli, Orlando, FL (US);
Morgan J. Thoma, Orlando, FL (US);
Agere Systems Inc., Allentown, PA (US);
Abstract
The present invention provides a process for fabricating merged integrated circuits on a semiconductor wafer substrate. The process comprises forming a gate oxide on the semiconductor wafer substrate, forming a first transistor having a first gate on the gate oxide, and forming a second transistor having a second gate on the same gate oxide. The first transistor is optimized to a first operating voltage by varying a physical property of the first gate, varying a first tub doping profile, or varying a first source/drain doping profile. The second transistor is optimized to a second operating voltage by varying a physical property of the second gate, varying a second tub doping profile, or varying a second source/drain doping profile of the second transistor. These physical characteristics may be changed in any combination or singly to achieve the determined optimization of the operating voltage of any given transistor.